The present invention relates to the field of instruction-controlled digital computers and specifically to the processing units of digital computers.
Instruction-controlled digital computers execute instructions to carry out desired information manipulations. A group of instructions form a program. A program has its instructions sequentially executed by a digital computer, one or more at a time, to carry out the desired manipulations.
High-speed digital computers generally include one or more storage units for storing information, I/O units for communicating with input/output devices, a console for operator communication with the digital computer, and a processor unit for instruction execution.
In typical digital computers, information is supplied to and from the input/output devices from and to the remainder of the system through storage units. Typically, instructions to be executed are fetched from the storage unit by the processor unit. The fetched instructions are decoded to form control signals for controlling the execution of the instructions and thus for controlling various operations throughout the computer.
In establishing an architecture for a digital computer, economy of cost and speed of instruction execution are paramount considerations. The cost of the computer is related to the cost of the "hardware", that is, to the number and type of circuits employed and is related to the cost of the "software", that is, to the cost of providing the programs which are run by the computer. The performance of the computer is related to the speed with which the system can execute programs. The cost/performance ratio represents a figure of merit for a computer system. The lower the cost/performance ratio, the better the computer.
Another consideration in establishing the architecture for a particular digital computer system is compatibility with other digital computers and software. If compatibility with prior systems can be maintained, the software or other parts of prior systems can be beneficially retained. If compatibility with future systems can be readily achieved, then the useful life of a particular system can be extended.
Compatibility must be determined with reference to both hardware and software. Hardware compatibility requires that the apparatus in one digital computer be able to perform the same functions, either directly or indirectly by emulation, as the apparatus in another digital computer. Software compatibility requires programs executable on one digital computer to be executable on another digital computer.
Frequently, one digital computer called the target computer, is defined with an architecture including a certain number of functions to be performed using a particular set of target instructions. Frequently, another digital computer, called a host computer, is defined with an architecture which is designed to be compatible with the target computer. For compatibility, the host computer must emulate the target computer and thereby perform the same functions as the target computer and in so doing must execute programs written using the target instruction set.
When a host computer is designed to emulate a target computer, the host computer may operate with greater performance than or may cost less than the target computer. Such a host computer is an improvement over the target computer.
The IBM 370 computers are frequently target computers to be emulated by compatible host computers. The 370 computers are programmed with the 370 instruction set. A compatible host computer adapted to emulate a 370 computer performs the previously written 370 target programs avoiding or minimizing the necessity of reprogramming.
Prior art host digital computers have typically been designed using microinstructions to control the host computer. Such host digital computers operate, under microinstruction control, to execute each target instruction. The execution of a target instruction in a host computer typically requires the execution of a sequence of microinstructions in the host computer. When the sequence of microinstructions is executed, the result is execution of the target instruction.
The performance of the host computer in executing the target instruction is determined in part by the architecture of the host computer. In general, the host computer operates to fetch each target instruction. The operation code (Op Code) from the target instruction is employed by the host computer to develop a sequencing path to the microinstructions necessary to execute the target instruction. The necessary microinstructions are generally contained in a number of subroutines each subroutine including a series of microinstructions. These subroutines must be accessed and executed to cause execution of the target instruction.
One way of accessing the microinstruction subroutines in the host computer is by accessing a series of subroutine calls from a series of indirect addresses stored in the low-order locations of a microstore. The OP CODE from the target instruction to be executed is used to address the low-order locations of the microstore. The low-order locations of the microstore are preloaded with indirect addresses to provide jumps to call subroutines. Each indirect address specifies the location of a call subroutine unique to a particular target instruction. The call subroutine in turn contains a series of subroutine addresses which are accessed in sequence to call the subroutines necessary for executing the target instruction. In such an indirect address implementation, the number of microinstructions necessary to execute each target instruction is excessive because of the necessity of obtaining first the indirect address and thereafter the subroutine call addresses. The indirect address step requires at least one cycle of the host computer for each execution of a target instruction.
Another way of accessing the microinstruction subroutines in the host computer is to employ a separate addressable storage unit as a hardware jump table. The jump table provides a microaddress for addressing the microstore. The Op Code from the target instruction addresses the jump table directly to obtain the microaddress of a calling subroutine. That microaddress is used directly to address the microstore to access the call subroutine. The call subroutine in turn contains a series of subroutine microaddresses which are accessed in sequence to call the subroutines necessary to execute the target instruction. The use of a hardware jump table avoids the need for an additional indirect address cycle and thereby saves at least one cycle of the host computer for each execution of a target instruction.
Although the use of a hardware jump table eliminates one cycle of the host computer for each target instruction execution, the hardware jump table still requires execution of a call subroutine. For each call subroutine, the host computer normally must execute at least one call microinstruction which undesirably requires at least one cycle of the host computer. Such host computer cycles allocated to call subroutines necessarily degrade performance of the host computer in the execution of target instructions.
In digital computers in general, the task of calling and returning from subroutines has been widely examined. Stack computers are one type of digital computer which minimize the performance degredation caused by subroutine calls and returns. Stack computers are described, for example, in the May, 1977 issue of COMPUTER, Volume 10, Number 5, published by the IEEE Computer Society. While stack computers may have some advantage in terms of the efficiency in subroutine control, they have not been entirely satisfactory for a number of reasons such as their incompatibility with many types of digital computers and software. Such stack computers are generally incompatible with target computers such as the IBM 370 computers.
In view of the above background, there is a need for an improved digital computer having the flexibility to perform as a compatible host computer which efficiently emulates one or more selected target computers and which operates with an improved cost/performance ratio.